Deep Submicron Challenges Term Paper by Champ

Deep Submicron Challenges
A discussion regarding the modern challenges of an engineer today.
# 98522 | 2,558 words | 5 sources | MLA | 2007 | US
Published on Oct 02, 2007 in Engineering (Electrical) , Engineering (Mechanical) , Engineering (General)


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Description:

This paper takes a look at IC and ASIC designers and discusses how, in the early 1980s, engineers had life a bit easier than engineers do today. The paper goes on to say that they did not have to deal with the tiniest of mechanisms, testing them, creating switches, circuits and memory from electrons and molecules. According to the paper, delay specifications for the early (multi- micron) technologies were elementary at best.

From the Paper:

"Engineering teams from major universities and corporations deal with specifics of design problems and engineering team coordination raises the overhead. The scale of the design has been decreasing, which also increases complexity, cost and testing difficulties. The architecture of the SOCs must change in how they are laid on the chip, as well as the materials that are being used in order to avoid the problems that were addressed earlier in this research. As new systems are needed to take advantage of advances in IC manufacturing technology, finer process geometries will provide the ability to manufacture more gates on a single die. Large systems in silicon have declined, due to physical design limitations and now more appropriate, expensive materials will replace silicon. There will be 1 billion transistors made in 2007 (Lai 27)."

Sample of Sources Used:

  • Agrawa,Vishwani and Bushnell, Michael. "27 Emerging Nanotechnology Devices." Deep Submicron VLSI Design by Tezaswi Raja - Trans-Meta Corp. 5/1/2006, <http://www.caip.rutgers.edu/~bushnell/dsmdesign/dsmwebpage.html>.
  • Gupta, Rajesh. "Deep-Submicron Challenges." EIC, Mar-Apr 2002.
  • Lai, Jordan "The Design Challenge for the Very Deep Submicron Technology." SMC, May 2003 <http://larc.ee.nthu.edu.tw/dtc/doc/seminar030523.pdf>.
  • Lin, Xi-Wei and Pramanik, Dipu, "Impact of Scaling on Design." Physical Design for Deep Submicron Processes, Semizone.com. 2006. <http://www.semizone.com/webcast/ >.
  • Maxfield and Montrose Interactive Inc. "Deep Submicron Delay Effects." 1998. <http://www.maxmon.com/default.htm>.

Cite this Term Paper:

APA Format

Deep Submicron Challenges (2007, October 02) Retrieved September 29, 2023, from https://www.academon.com/term-paper/deep-submicron-challenges-98522/

MLA Format

"Deep Submicron Challenges" 02 October 2007. Web. 29 September. 2023. <https://www.academon.com/term-paper/deep-submicron-challenges-98522/>

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